525.742.31: SOC FPGA Design Lab

Announcements:

Questions regarding class material and assignments should be directed to the mailing list through socfpgalab@googlegroups.com. This forum will be monitored by the instructors. Use of this forum allows you to be assured an answer even if one instructor is currently unavailable. Note that you must join the forum to be allowed to post to the group.

Lecture Notes:

Lectures provided in PDF format.

Homework:

When the laboratory assignment asks for an electronic project submission, this is done via. Sakai

Laboratory assignments and associated links:

Lab 1 (Tutorials / Synchronous Design Refresher)
Lab 2 (Audio)

Operational Sample Bitfile (To see an example of the lab in operation)
Length 48 Tone This should be a Sinewave at Fs/48
Cowbell Effect The sound of a single cowbell hit

Lab 3 Tutorial (Timer)

Lab 3 (Ethernet Subsystem)

Example Lab 3 bitfile

Lab 4 (End-to-End Data Transfer)

Lab 4 bitfile (This will generate simulated data.)
Lab 4 Matlab code and example data file

Lab 5 (FIR Filtering for Channel Selection)

collect_data_real.m (This will collect streaming UDP in real-time.)

Lab 6 (SDR, Complete)

Documentation

Datasheets for the ATLYS Board Hardware:

Files

Programs available to help with labs:

Bray's Terminal: A Terminal Program that will print in hex and do lots of nice things for easy debugging
NCH Tone Generator : A Simple Tone Generator for audio based labs. Source: http://www.nch.com.au
netcat : Ethernet swiss army knife.
WireSHARK

DVI / HDMI Sample Project

VHDL Modules, ISE Projects, C Libraries, etc. for Tutorials/Labs: